The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a plurality of basic blocks, at least one of which is selectively activated by first and second selective signals.
FIG. 1 is a diagram illustrative of a first conventional structure of a semiconductor integrated circuit having a plurality of basic blocks to be selectively activated by first and second selective signals. The first conventional structure of a semiconductor integrated circuit has an N.times.M array of basic blocks 101, at least one of which is selected so that the number "L" of control signals are transmitted to the selected basic block for controlling order and time differences for activation or inactivation to component blocks which form the selected basic block. First and second block selective decoders 102 ands 103 are provided which generate first and second block selective signals which are to be transmitted in X-direction and Y-direction.
The selection of the individual basic blocks 101 are accomplished as follows. Each of the basic blocks 101 receives both the first and second selective signals for activation or inactivation to accomplish AND-logic of the first and second selective signals. If the basic block 101 receives the both the first and second selective signals for activation, then the basic block 101 is activated. A control signal generator circuit 104 is provided which generates the number "L" of control signals which are to be transmitted to the activated basic block 101. The control signals are required to be activated for a time period which includes a time period of the activation of the first and second selective signals. The first and second selective signals were activated before the control signals have been activated, and then the control signals are inactivated and subsequently the first and second selective signals are inactivated.
FIG. 2 is a diagram illustrative of a second conventional structure of a semiconductor integrated circuit of a dynamic random access memory to explain a method of transmission of control signals. This second conventional structure is almost the same as the above first conventional structure. The following descriptions with reference to FIG. 2 is disclosed in JSSCC, vol. 28, No. 11, pp. 1092-1098. The second conventional structure of the dynamic random access memory has an N.times.M array of basic blocks 101, at least one of which is selected so that the number "L" of control signals are transmitted to the selected basic block for controlling order and time differences for activation or inactivation to component blocks which form the selected basic block. First and second selective signal generator circuits 102 and 103 are provided which generate first and second block selective signals which are to be transmitted in X-direction and Y-direction. If the activation signal to the sense amplifier is transmitted, the second selective signal generator circuit 103 is operated to activate block selective signals RSL0 and RSL1 to be transmitted on second lines 2 which extend in Y-direction. After a predetermined time has passed from the activation of the block selective signals RSL0 and RSL1, then the first selective signal generator circuit 102 is operated to activate block selective signals SSL0 and SSL1 to be transmitted on first lines 1 which extend in X-direction. A wait time is defined to be a time until the block selective signals SSL0 and SSL1 are activated after the block selective signals RSL0 and RSL1 have been activated. This wait time depends upon a time which is defined to be a time until activation of all of the basic blocks is completed after the activation to the block selective signals RSL0 and RSL1 has been commenced. Each of the above block selective signals SSL0 and SSL1 includes not only an information of selecting blocks in X-direction but also another information of controlling the activation to the sense amplifier. The block selective signals SSL0 and SSL1 are AND-logic signals of the signals of selecting blocks in X-direction and the signals of controlling the activation to the sense amplifier. Namely, the control signals are transmitted together with one of the block selective signals. The reason why the control signals are transmitted together with one of the block selective signals are to reduce the number of the necessary lines which vary in potential due to signal transmissions.
The above conventional structure has the following problems. The necessary wait time is increased by the increase in scale of the semiconductor integrated circuit, and further the increase in the necessary wait time also increase a latency and a cycle time. The increase in latency of the circuit due to the increase in the wait time will be described. At a time T0, the block selective signals to be transmitted in Y-direction are generated by the second selective decoder 103. A delay T1 in signal transmission on the line 1 extending in X-direction causes an extension of the necessary time for completion of transmissions of the block selective signals in Y-direction to all of the basic blocks. In order to complete transmission of the block selective signals to all of the basic blocks prior to the transmission of he control signals, at a time T0+T1 which is the sum of the above time T0 and the wait time T1, control signals to the basic blocks are outputted from the circuit 103 together with the block selective signals in Y-direction. Assuming that a delay time in transmission of the signals on the lines 2 is T2, the necessary time for completion of the transmission of the control signals to all of the basic blocks is T0+T1+T2. The wait time T1 and the delay time T2 depend upon the circuit scale and increase as the circuit scale creases.
The following descriptions will focus on the increase in the cycle time due to the increase in wait time. A time during which the basic blocks remain activated by the number "L" of the control signals is defined to be T3. Since the time of commencement of the activation to the control signals in the circuit 103 is T0+T1, the time of inactivation to all of the control signals in the circuit 103 is T0+T1+T3, and a time of completion of transmission of the inactivated control signals to all of the basic blocks is T0+T1+T2+T3, where the T2 is the delay in transmission of the line 2.
In all of the basic blocks, it is necessary to inactivate the block selective signals after the inactivated control signals have been transmitted, for which purpose, at the time of summing the wait time and the time T0+T1+T3 having just inactivated all of the control signals, or the time T0+T1+T2+T3, the block selective signals to be transmitted in Y-direction are inactivated.
It is permitted to activate the block selective signals to be transmitted in Y-direction in the next cycle but after the time T0+T1+T2+T3, for which reason the minimum cycle time is defined to be T1+T2+T3, wherein the wait times T1 and T2 depend on the circuit scale and increase as the circuit scale creases.
In the above circumstances, it had been required to develop a novel semiconductor integrated circuit free from the above problem.